View IS65WV25616DBLL-55CTLA3_6987139.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

integrated silicon solution, inc. www.issi.com 1 rev. d 06/19/2013 copyright ? 2013 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this specifcation and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtain the lat - est version of this device specifcation before relying on any published information and before placing orders for products. integrated silicon solution, inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be ex - pected to cause failure of the life support system or to signifcantly affect its safety or effectiveness. products are not authorized for use in such applications unless integrated silicon solution, inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of integrated silicon solution, inc is adequately protected under the circumstances is62wv25616dall/dbll, is65wv25616dbll 256k x 16 low voltage, ultra low power cmos static sram features ? high-speed access time: 35, 45, 55 ns ? cmos low power operation 30 mw (typical) operating 6 w (typical) cmos standby ? ttl compatible interface levels ? single power supply 1.65v--2.2v v dd (is62wv25616dall) 2.5v--3.6v v dd (is62/65wv25616dbll) ? fully static operation: no clock or refresh required ? three state outputs ? data control for upper and lower bytes ? industrial and automotive temperature support ? lead-free available ? 2 cs option available description the issi is62wv25616dall and is62/65wv25616dbll are high-speed, low power, 4m bit srams organized as 256k words by 16 bits. it is fabricated using issi 's high- performance cmos technology. this highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. when cs1 is high (deselected) or when cs2 is low (deselcted) or when cs1 is low, cs2 is high and both lb and ub are high, the device assumes a standby mode at which the power dissipation can be reduced down with cmos input levels. easy memory expansion is provided by using chip enable and output enable inputs. the active low write enable (we) controls both writing and reading of the memory. a data byte allows upper byte ( ub) and lower byte (lb ) access. the is62wv25616dall and is62/65wv25616dbll are packaged in the jedec standard 44-pin tsop (type ii) and 48-pin mini bga (6mmx8mm). functional block diagram june 2013 a0-a17 cs1 cs2 oe we 256k x 16 memory array decoder column i/o control circuit gnd v dd i/o data circuit i/o0-i/o7 lower byte i/o8-i/o15 upper byte ub lb
is62wv25616dall/dbll, is65wv25616dbll 2 integrated silicon solution, inc. www.issi.com rev. d 06/19/2013 pin descriptions a0-a17 address inputs i/o0-i/o15 data inputs/outputs cs1, cs2 chip enable input oe output enable input we write enable input lb lower-byte control (i/o0-i/o7) ub upper-byte control (i/o8-i/o15) nc no connection v dd power gnd ground 44-pin mini tsop (type ii) (package code t) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 a4 a3 a2 a1 a0 cs1 i/o0 i/o1 i/o2 i/o3 v dd gnd i/o4 i/o5 i/o6 i/o7 we a16 a15 a14 a13 a12 a5 a6 a7 oe ub lb i/o15 i/o14 i/o13 i/o12 gnd v dd i/o11 i/o10 i/o9 i/o8 nc a8 a9 a10 a11 a17 pin configurations 48- ball mini bga (6mm x 8mm) (package code b) 1 2 3 4 5 6 a b c d e f g h lb oe a0 a1 a2 nc i/o 8 ub a3 a4 csi i/o 0 i/o 9 i/o 10 a5 a6 i/o 1 i/o 2 gnd i/o 11 a17 a7 i/o 3 vdd vdd i/o 12 nc a16 i/o 4 gnd i/o 14 i/o 13 a14 a15 i/o 5 i/o 6 i/o 15 nc a12 a13 we i/o 7 nc a8 a9 a10 a11 nc 48-pin mini bga (6mm x 8mm)* 2 cs option (package code b2) 1 2 3 4 5 6 a b c d e f g h lb oe a0 a1 a2 cs2 i/o 8 ub a3 a4 cs1 i/o 0 i/o 9 i/o 10 a5 a6 i/o 1 i/o 2 gnd i/o 11 a17 a7 i/o 3 vdd vdd i/o 12 nc a16 i/o 4 gnd i/o 14 i/o 13 a14 a15 i/o 5 i/o 6 i/o 15 nc a12 a13 we i/o 7 nc a8 a9 a10 a11 nc *available upon request
integrated silicon solution, inc. www.issi.com 3 rev. d 06/19/2013 is62wv25616dall/dbll, is65wv25616dbll absolute maximum ratings (1) symbol parameter value unit v term terminal voltage with respect to gnd C0.5 to v dd + 0.5 v v dd v dd relates to gnd C0.3 to 4.0 v t stg storage temperature C65 to +150 c p t power dissipation 1.0 w notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. capacitance (1,2) symbol parameter conditions max. unit c in input capacitance v in = 0v 6 pf c i/o input/output capacitance v out = 0v 8 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25c, f = 1 mhz, v dd = 3.3v. truth table i/o pin mode we cs1 cs2 oe lb ub i/o0-i/o7 i/o8-i/o15 v dd current not selected x h x x x x high-z high-z i sb 1 , i sb 2 x x l x x x high-z high-z i sb 1 , i sb 2 x x x x h h high-z high-z i sb 1 , i sb 2 output disabled h l h h l x high-z high-z i cc h l h h x l high-z high-z i cc read h l h l l h d out high-z i cc h l h l h l high-z d out h l h l l l d out d out write l l h x l h d in high-z i cc l l h x h l high-z d in l l h x l l d in d in
is62wv25616dall/dbll, is65wv25616dbll 4 integrated silicon solution, inc. www.issi.com rev. d 06/19/2013 ac test loads figure 1. r1 5 pf including jig and scope r2 output vtm figure 2. ac test conditions parameter unit unit unit (2.3v-3.6v) (3.3v + 5%) (1.65v-2.2v) input pulse level 0.4v to v dd - 0.3v 0.4v to v dd - 0.3v 0.4v to v dd - 0.3v input rise and fall times 1v/ ns 1v/ ns 1v/ ns input and output timing vdd /2 vdd + 0.05 0.9v and reference level (v ref ) 2 output load see figures 1 and 2 see figures 1 and 2 see figures 1 and 2 r1 ( ? ) 1005 1213 13500 r2 ( ? ) 820 1378 10800 v tm (v) 3.0v 3.3v 1.8v r1 30 pf including jig and scope r2 output vtm
integrated silicon solution, inc. www.issi.com 5 rev. d 06/19/2013 is62wv25616dall/dbll, is65wv25616dbll dc electrical characteristics (over operating range) v dd = 2.3v-3.6v symbol parameter test conditions min. max. unit v oh output high voltage v dd = min., i oh = C1.0 ma 1.8 v v ol output low voltage v dd = min., i ol = 2.1 ma 0.4 v v ih input high voltage 2.0 v dd + 0.3 v v il input low voltage (1) C0.3 0.8 v i li input leakage gnd v in v dd C1 1 a i lo output leakage gnd v out v dd , outputs disabled C1 1 a note: 1. v il ( min.) = C0.3v dc; v il (min.) = C2.0v ac (pulse width < 10 ns). not 100% tested. v ih ( max.) = v dd + 0.3v dc; v ih ( max.) = v dd + 2.0v a c (pulse width < 10 ns). not 100% tested. dc electrical characteristics (over operating range) v dd = 3.3v + 5% symbol parameter test conditions min. max. unit v oh output high voltage v dd = min., i oh = C1 ma 2.4 v v ol output low voltage v dd = min., i ol = 2.1 ma 0.4 v v ih input high voltage 2 v dd + 0.3 v v il input low voltage (1) C0.3 0.8 v i li input leakage gnd v in v dd C1 1 a i lo output leakage gnd v out v dd , outputs disabled C1 1 a note: 1. v il ( min.) = C0.3v dc; v il (min.) = C2.0v ac (pulse width < 10 ns). not 100% tested. v ih ( max.) = v dd + 0.3v dc; v ih ( max.) = v dd + 2.0v a c (pulse width < 10 ns). not 100% tested. dc electrical characteristics (over operating range) v dd = 1.65v-2.2v symbol parameter test conditions v dd min. max. unit v oh output high voltage i oh = -0.1 ma 1.65-2.2v 1.4 v v ol output low voltage i ol = 0.1 ma 1.65-2.2v 0.2 v v ih input high voltage 1.65-2.2v 1.4 v dd + 0.2 v v il (1) input low voltage 1.65-2.2v C0.2 0.4 v i li input leakage gnd v in v dd C1 1 a i lo output leakage gnd v out v dd , outputs disabled C1 1 a note: 1. v il ( min.) = C0.3v dc; v il (min.) = C2.0v ac (pulse width < 10 ns). not 100% tested. v ih ( max.) = v dd + 0.3v dc; v ih ( max.) = v dd + 2.0v a c (pulse width < 10 ns). not 100% tested.
is62wv25616dall/dbll, is65wv25616dbll 6 integrated silicon solution, inc. www.issi.com rev. d 06/19/2013 power supply characteristics (1) (over operating range) -35 -45 -55 symbol parameter test conditions min. max. min. max. min. max. unit i cc v dd dynamic operating v dd = max., com. 20 15 15 ma supply current i out = 0 ma, f = f max ind./auto a1 25 18 15 ce = v il auto. a3 30 25 25 v in v dd C 0.3v, or typ. (2) 10 v in 0.4v i cc 1 operating v dd = max., com. 3 3 3 ma supply current i out = 0 ma, f = 0 ind./auto a1 3 3 3 ce = v il auto. a3 3 3 3 v in v dd C 0.3v, or v in 0.4v i sb 2 cmos standby v dd = max., com. 5 5 5 a current (cmos inputs) cs1 v dd C 0.2v, ind./ auto a1 10 10 10 cs2 0.2v, auto. a3 30 30 30 v in v dd C 0.2v, or typ. (2) 2 v in 0.2v, f = 0 or ulb control v dd = max., cs1 = v il , cs2=v ih v in 0.2v, f = 0; ub / lb = v dd C 0.2v note: 1. at f = f max , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. typical values are measured at v dd = 3.0v, t a = 25 o c and not 100% tested. operating range ( v dd ) ran ge ambient temperatur e v dd (45 n s ) v dd (35 n s ) commercial 0c to +70c 2.3v-3.6v 3.3v+5% industrial C40c to +85c 2.3v-3.6v 3.3v+5% automotive (a1) C40c to +85c 2.3v-3.6v 3.3v+5% operating range ( v dd ) r ange ambient temperature v dd s peed commercial 0c to +70c 1.65v-2.2v 45ns industrial C40c to +85c 1.65v-2.2v 55ns automotive C40c to +125c 1.65v-2.2v 55ns operating range ( v dd ) rang e ambient temperature v dd (45 n s ) automotive (a3) C40c to +125c 2.3v-3.6v
integrated silicon solution, inc. www.issi.com 7 rev. d 06/19/2013 is62wv25616dall/dbll, is65wv25616dbll read cycle switching characteristics (1) (over operating range) 35 ns 45 ns 55 ns symbol parameter min. max. min. max. min. max. unit t rc read cycle time 35 45 55 ns t aa address access time 35 45 55 ns t oha output hold time 10 10 10 ns t a cs 1/ t a cs 2 cs1/cs2 access time 35 45 55 ns t doe oe access time 10 20 25 ns t hzoe (2) oe to high-z output 0 10 0 15 0 20 ns t lzoe (2) oe to low-z output 3 5 5 ns t hzcs 1/ t hzcs 2 (2) cs1/cs2 to high-z output 0 10 0 15 0 20 ns t lzcs 1/ t lzcs 2 (2) cs1/cs2 to low-z output 5 5 10 ns t ba lb, ub access time 35 45 55 ns t hzb lb, ub to high-z output 0 15 0 15 0 20 ns t lzb lb, ub to low-z output 0 0 0 ns notes: 1. test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9v/1.5v, input pulse levels of 0.4 to v dd -0.2v/v dd -0.3v and output loading specifed in figure 1. 2. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested.
is62wv25616dall/dbll, is65wv25616dbll 8 integrated silicon solution, inc. www.issi.com rev. d 06/19/2013 data valid previous data valid t aa t oha t oha t rc d out address ac waveforms read cycle no. 1 (1,2) (address controlled) (cs1 = oe = v il , cs2 = we = v ih , ub or lb = v il ) t rc t oha t aa t doe t lzoe t ace1/ t ace2 t lzce1/ t lzce2 t hzoe high-z data valid t hzcs1/ t hzcs2 address oe cs1 cs2 dout lb , ub t hzb t ba t lzb ac waveforms read cycle no. 2 (1,3) (cs1, cs2, oe, and ub/lb controlled) notes: 1. we is high for a read cycle. 2. the device is continuously selected. oe, cs1, ub, or lb = v il . c s2= we =v ih . 3. address is valid prior to or coincident with cs1 low transition.
integrated silicon solution, inc. www.issi.com 9 rev. d 06/19/2013 is62wv25616dall/dbll, is65wv25616dbll write cycle switching characteristics (1,2) (over operating range) 35 ns 45 ns 55 ns symbol parameter min. max. min. max. min. max. unit t wc w rite cycle time 35 45 55 ns t scs 1/ t scs 2 cs1/cs2 to write end 25 35 45 ns t aw address setup time to write end 25 35 45 ns t ha address hold from write end 0 0 0 ns t sa address setup time 0 0 0 ns t pwb lb, ub valid to end of write 25 35 45 ns t pwe we pulse width 25 35 40 ns t sd data setup to write end 20 20 25 ns t hd data hold from write end 0 0 0 ns t hzwe (3) we low to high-z output 10 20 20 ns t lzwe (3) we high to low-z output 3 5 5 ns notes: 1. test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9v/1.5v, input pulse levels of 0.4v to v dd -0.2v/v dd -0.3v and output loading specifed in figure 1. 2. the internal write time is defned by the overlap of cs1 low, cs2 high and ub or lb, and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falling edge of the signal that terminates the write. 3. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested.
is62wv25616dall/dbll, is65wv25616dbll 10 integrated silicon solution, inc. www.issi.com rev. d 06/19/2013 ac waveforms write cycle no. 1 (1,2) (cs1 controlled, oe = high or low) data-in vali d data undefined t wc t scs1 t scs2 t aw t ha t pwe t hzwe high-z t lzwe t sa t sd t hd address cs1 cs2 we dout din lb, ub t pwb notes: 1. write is an internally generated signal asserted during an overlap of the low states on the cs1 , cs2 and we inputs and at least one of the lb and ub inputs being in the low state. 2. write = (cs1) [ (lb) = (ub) ] (we).
integrated silicon solution, inc. www.issi.com 11 rev. d 06/19/2013 is62wv25616dall/dbll, is65wv25616dbll data-in vali d data undefined t wc t scs1 t scs2 t aw t ha t pwe t hzwe high-z t lzwe t sa t sd t hd address oe cs1 cs2 we lb, ub dout din ac waveforms write cycle no. 2 (we controlled: oe is high during write cycle)
is62wv25616dall/dbll, is65wv25616dbll 12 integrated silicon solution, inc. www.issi.com rev. d 06/19/2013 data-in vali d data undefined t wc t scs1 t scs2 t aw t ha t pwe t hzwe high-z t lzwe t sa t sd t hd address oe cs1 cs2 we lb, ub dout din ac waveforms write cycle no. 3 (we controlled: oe is low during write cycle)
integrated silicon solution, inc. www.issi.com 13 rev. d 06/19/2013 is62wv25616dall/dbll, is65wv25616dbll data undefined t wc address 1 address 2 t wc high-z t pbw word 1 low word 2 t hd t sa t hzwe address cs1 ub, lb we d out d in oe data in valid t lzwe t sd t pbw data in valid t sd t hd t sa t ha t ha ub_cswr4.eps high cs2 ac waveforms write cycle no. 4 (ub/lb controlled)
is62wv25616dall/dbll, is65wv25616dbll 14 integrated silicon solution, inc. www.issi.com rev. d 06/19/2013 data retention waveform (cs1 controlled) v dd cs1 v dd - 0.2v t sdr t rdr v dr cs1 gnd data retention mode data retention switching characteristics symbol parameter test condition min. max. unit v dr v dd for data retention see data retention waveform 1.2 3.6 v i dr data retention current v dd = 1.2v, cs1 v dd C 0.2v com. 3 a ind. 7 auto. 20 typ. (1) 1 t sdr data retention setup time see data retention waveform 0 ns t rdr recovery time see data retention waveform t rc ns note: 1. typical values are measured at v dd = 3.0v, t a = 25 o c and not 100% tested. data retention waveform (cs2 controlled) v dd cs2 0.2v t sdr t rdr v dr 0.4v ce2 gnd data retention mode
integrated silicon solution, inc. www.issi.com 15 rev. d 06/19/2013 is62wv25616dall/dbll, is65wv25616dbll is62wv25616dbll (2.3v - 3.6v) industrial range: C40c to +85c speed (ns) order part no. package 45 is62wv25616dbll-45ti tsop is62wv25616dbll-45tli tsop, lead-free 45 is62wv25616dbll-45bi mini bga (6mmx8mm) is62wv25616dbll-45bli mini bga (6mmx8mm), lead-free 55 is62wv25616dbll-55tli tsop, lead-free ordering information is62wv25616dall (1.65v-2.2v) commercial range: 0c to +70c speed (ns) order part no. package 70 is62wv25616dall-55tl tsop, lead-free industrial range: C40c to +85c speed (ns) order part no. package 55 is62wv25616dall-55ti tsop is62wv25616dall-55tli tsop, lead-free 55 is62wv25616dall-55bi mini bga (6mmx8mm) is62wv25616dall-55bli mini bga (6mmx8mm), lead-free is65wv25616dbll (2.3v - 3.6v) automotive (a1) range: C40c to +85c speed (ns) order part no. package 45 is65wv25616dbll-45ctla1 tsop, lead-free, copper leadframe automotive (a3) range: C40c to +125c speed (ns) order part no. package 55 IS65WV25616DBLL-55CTLA3 tsop, lead-free, copper leadframe
is62wv25616dall/dbll, is65wv25616dbll 16 integrated silicon solution, inc. www.issi.com rev. d 06/19/2013 2. dimension d and e1 do not include mold protrusion. 3. dimension b does not include dambar protrusion/intrusion. 1. controlling dimension : mm note : 06/04/2008 package outline
integrated silicon solution, inc. www.issi.com 17 rev. d 06/19/2013 is62wv25616dall/dbll, is65wv25616dbll 2. reference document : jedec mo-207 1. controlling dimension : mm . note : 08/12/2008 package outline

▲Up To Search▲

Price & Availability of IS65WV25616DBLL-55CTLA3

	To Download IS65WV25616DBLL-55CTLA3 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .